Samsung semiconductor K4H560838F-TCCC
256Mb F-die DDR400 SDRAM Specification
| Part No. | K4H560838F-TCCC |
|---|---|
| Datasheet | K4H560838F-TCCC Download |
| Manufacturer |  Samsung semiconductor |
| Description | 256Mb F-die DDR400 SDRAM Specification |
| Buy | Stock & Price |
FEATURES
● 200MHz Clock, 400Mbps data rate.● VDD= +2.6V + 0.10V, VDDQ= +2.6V + 0.10V
● Double-data-rate architecture; two data transfers per clock cycle
● Bidirectional data strobe(DQS)
● Four banks operation
● Differential clock inputs(CK and CK)
● DLL aligns DQ and DQS transition with CK transition
● MRS cycle with address key programs -. Read latency 3 (clock) for DDR400 , 2.5 (clock) for DDR333 -. Burst length (2, 4, 8) -. Burst type (sequential & interleave)
● All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
● Data I/O transactions on both edges of data strobe
● Edge aligned data output, center aligned data input
● LDM,UDM for write masking only (x16)
● Auto & Self refresh
● 7.8us refresh interval(8K/64ms refresh)
● Maximum burst refresh cycle : 8
● 66pin TSOP II package DDR SDRAM Ordering Information Part No. K4H560838F-TCCC K4H560838F-TCC4 K4H561638F-TCCC K4H561638F-TCC4 16M x 16 32M x 8 Org. Max Freq. CC(DDR400@CL=3) C4(DDR400@CL=3) CC...
