Samsung semiconductor K4M51163LC
The K4M51163LC is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 8,388,608 words by 16 bits, fabricated with SAMSUNG's high performance CMOS technology.| Part No. | K4M51163LC |
|---|---|
| Datasheet | K4M51163LC Download |
| Manufacturer |  Samsung semiconductor |
| Description | 8M x 16Bit x 4 Banks Mobile SDRAM |
| Buy | Stock & Price |
FEATURES
● VDD/VDDQ = 2.5V/2.5V● LVCMOS compatible with multiplexed address.
● Four banks operation.
● MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave).
● EMRS cycle with address key programs.
● All inputs are sampled at the positive going edge of the system clock.
● Burst read single-bit write operation.
● Special Function Support. -. PASR (Partial Array Self Refresh). -. Internal TCSR (Temperature Compensated Self Refresh)
● DQM for masking.
● Auto refresh.
● 64ms refresh period (8K cycle).
● Commercial Temperature Operation (-25°C ~ 70°C).
● Extended Temperature Operation (-25°C ~ 85°C).
● 1 /CS Support.
● 54Balls FBGA ( -RXXX -Pb, -BXXX -Pb Free). Mobile SDRAM
GENERAL DESCRIPTION
Synchronous design allows precise cycle control with the use of system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
