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K4S281632D-L1L - 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL

This page provides the datasheet information for the K4S281632D-L1L, a member of the K4S 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL family.

Description

The K4S281632D is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology.

Features

  • JEDEC standard 3.3V power supply.
  • LVTTL compatible with multiplexed address.
  • Four banks operation.
  • MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave).
  • All inputs are sampled at the positive going edge of the system clock.
  • Burst read single-bit write operation.
  • DQM for masking.
  • Auto & self refresh.
  • 64ms refresh period (4K cycle.

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Datasheet preview – K4S281632D-L1L

Datasheet Details

Part number K4S281632D-L1L
Manufacturer Samsung Semiconductor
File Size 112.04 KB
Description 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
Datasheet download datasheet K4S281632D-L1L Datasheet
Additional preview pages of the K4S281632D-L1L datasheet.

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Full PDF Text Transcription

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K4S281632D CMOS SDRAM 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL Rev. 0.1 Sept. 2001 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.1 Sept. 2001 K4S281632D Revision History Revision 0.0 (Mar. 06, 2001) Revision 0.1 (Sep. 06, 2001) • • CMOS SDRAM Redefined IDD1 & IDD4 in DC Characteristics Changed the Notes in Operating AC Parameter. < Before > 5. For 1H/1L, tRDL=1CLK and tDAL=1CLK+tRP is also supported . SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP. < After > 5.In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP. Rev. 0.1 Sept. 2001 K4S281632D 2M x 16Bit x 4 Banks Synchronous DRAM FEATURES • JEDEC standard 3.
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