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K4S281633D-N1L - 8Mx16 SDRAM 54CSP

General Description

The K4S281633D is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology.

Key Features

  • 3.0V & 3.3V power supply.
  • LVTTL compatible with multiplexed address.
  • Four banks operation.
  • MRS cycle with address key programs. -. CAS latency (1 & 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave).
  • All inputs are sampled at the positive going edge of the system clock.
  • Burst read single-bit write operation.
  • DQM for masking.
  • Auto refresh.
  • 64ms refresh period (4K cycle.

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Other Datasheets by Samsung Semiconductor

Part Number Description
K4S281633D-N1H 8Mx16 SDRAM 54CSP
K4S281633D-N75 8Mx16 SDRAM 54CSP
K4S281633D-RL 8Mx16 SDRAM 54CSP
K4S281632B 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
K4S281632B-N 2M x 16Bit x 4 Banks Synchronous DRAM in sTSOP

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Preliminary K4S281633D-RL(N) CMOS SDRAM 8Mx16 SDRAM 54CSP (V DD/V DDQ 3.0V/3.0V & 3.3V/3.3V) Revision 0.6 November 2001 Rev. 0.6 Nov. 2001 Preliminary K4S281633D-RL(N) Revision History Revision 0.0 (February 21. 2001, Target) CMOS SDRAM • First generation of 128Mb Low Power SDRAM without special function (V DD 3.0V, V DDQ 3.0V) Revision 0.1 (June 4. 2001, Target) • Addition of DC Current value. Revision 0.2 (June 20. 2001, Target) • Changed device name from low power sdram to mobile dram. Revision 0.3 (August 1. 2001, Target) • Change of tSAC from 6ns to 6.5ns in case of -1L part, from 7ns to 7.5ns in case of -15 part. • Change of tOH from 3ns to 3.5ns. • Change V IH min. from 2.0 V to 0.8xVDDQ and VOH min. from 2.4V to 0.9xVDDQ. Revision 0.4 (October 6.