K4S511632B-TCL75 Datasheet | Samsung Semiconductor

FEATURES - JEDEC standard 3.3V power supply - LVTTL patible with multiplexed address - Four banks operation - MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8) -. Burst type (Sequential & Interleave) - All inputs are sampled at the positive going edge of the system clock. - Burst read single-bit write operation - DQM (x4,x8) & L(U)DQM (x16) for masking - Auto & self refresh - 64ms refresh period (8K Cycle) GENERAL DESCRIPTION The K4S510432B / K4S510832B / K4S511632B is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 33,554,432 words by 4 bits / 4 x 16,777,216 words by 8 bits / 4 x 8,388,608 words by 16 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. Ordering Information Part No. K4S510432B-TC(L)75 K4S510832B-TC(L)75 K4S511632B-TC(L)75 Orgainization 128Mb x 4 (CL=3) 64Mb x 8 (CL=3) 32Mb x 16 (CL=3) Max Freq. 133MHz 133MHz 133MHz LVTTL 54pin TSOP(II) Interface Package Organization 128Mx4 64Mx8 32Mx16 Row Address A0~A12 A0~A12 A0~A12 Column Address A0-A9, A11, A12 A0-A9, A11 A0-A9 Row & Column address configuration Rev. 1.1 February 2004 SDRAM 512Mb B-die (x4, x8, x16) Package Physical Dimension CMOS SDRAM 0~8°C 0.25 TYP 0.010 #54 #28 0.45~0.75 0.018~0.030 0.05 MIN 0.002 ( 0.50 ) 0.020 11.76±0.20 0.463±0.008 #1 22.62 MAX 0.891 22.22 0.875 0.10 MAX 0.004 ( 0.71 ) 0.028 ± 0.10 ± 0.004 #27 0.21 0.008 ± 0.05 ± 0.002 1.00 0.039 ± 0.10 ± 0.004 0.30 -0.05 0.004 0.012 + -0.002 +0.10 0.80 0.0315 54Pin TSOP(II) Package Dimension Rev. 1.1 February 2004 10.16 0.400 0.125+0.075 -0.035 0.005+0.003 -0.001 1.20 MAX 0.047 SDRAM 512Mb B-die (x4, x8,...