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K4S561633C-R(B)L/N/P
CMOS SDRAM
16Mx16 SDRAM 54CSP
(VDD/VDDQ 3.0V/3.0V or 3.3V/3.3V)
Revision 1.4 December 2002
Rev. 1.4 Dec. 2002
K4S561633C-R(B)L/N/P
4M x 16Bit x 4 Banks Synchronous DRAM in 54CSP
FEATURES
• 3.0V & 3.3V power supply. • LVCMOS compatible with multiplexed address. • Four banks operation. • MRS cycle with address key programs. -. CAS latency (1 & 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave). • All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation. • DQM for masking • Auto refresh. • 64ms refresh period (8K cycle). • Commercial Temperature Operation (-25° C ~ 70 °C). Extended Temperature Operation ( -25° C ~ 85 °C). Inderstrial Temperature Operation ( -40° C ~ 85° C).