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K4S640832C - 64Mbit SDRAM 2M x 8Bit x 4 Banks Synchronous DRAM LVTTL

General Description

The K4S640832C is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 8 bits, fabricated with SAMSUNG′s high performance CMOS technology.

Key Features

  • JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst read single-bit write operation DQM for masking Auto & self refresh 64ms refresh period (4K Cycle) CMOS SDRAM.

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Other Datasheets by Samsung Semiconductor

Part Number Description
K4S640832D 64Mbit SDRAM 2M x 8Bit x 4 Banks Synchronous DRAM LVTTL
K4S640832E 64Mbit SDRAM 2M x 8Bit x 4 Banks Synchronous DRAM LVTTL
K4S640832E-TC1H 64Mbit SDRAM 2M x 8Bit x 4 Banks Synchronous DRAM LVTTL
K4S640832E-TC1L 64Mbit SDRAM 2M x 8Bit x 4 Banks Synchronous DRAM LVTTL
K4S640832E-TC75 64Mbit SDRAM 2M x 8Bit x 4 Banks Synchronous DRAM LVTTL

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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K4S640832C CMOS SDRAM 64Mbit SDRAM 2M x 8Bit x 4 Banks Synchronous DRAM LVTTL Revision 0.1 Oct. 1999 * Samsung Electronics reserves the right to change products or specification without notice. Rev.0.1 Oct.1999 K4S640832C Revision History Revision 0.1 (Oct. 02, 1999) • Changed misprinted speed bining from -75 to -70. CMOS SDRAM Rev.0.1 Oct.1999 K4S640832C 2M x 8Bit x 4 Banks Synchronous DRAM FEATURES • • • • JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -.