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K6R1004C1C - High-Speed CMOS Static RAM

General Description

The K6R1004C1C is a 1,048,576-bit high-speed Static Random Access Memory organized as 262,144 words by 4 bits.

The K6R1004C1C uses 4 common input and output lines and has an output enable pin which operates faster than address access time at read cycle.

Key Features

  • Fast Access Time 10,12,15ns(Max. ).
  • Low Power Dissipation Standby (TTL) : 30mA(Max. ) (CMOS) : 5mA(Max. ) 0.5mA(Max. ) L-Ver. only Operating K6R1004C1C-10 : 75mA(Max. ) K6R1004C1C-12 : 70mA(Max. ) K6R1004C1C-15 : 68mA(Max. ).
  • Single 5.0V±10% Power Supply.
  • TTL Compatible Inputs and Outputs.
  • I/O Compatible with 3.3V Device.
  • Fully Static Operation - No Clock or Refresh required.
  • Three State Outputs.
  • 2V Minimum Data Retention: L-ver.

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Full PDF Text Transcription for K6R1004C1C (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for K6R1004C1C. For precise diagrams, and layout, please refer to the original PDF.

www.DataSheet4U.com PRELIMINARY PRELIMINARY CMOS SRAM K6R1004C1C-C/C-L, K6R1004C1C-I/C-P Document Title 256Kx4 Bit (with OE) High-Speed CMOS Static RAM(5.0V Operating). R...

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tle 256Kx4 Bit (with OE) High-Speed CMOS Static RAM(5.0V Operating). Revision History Rev. No. Rev. 0.0 Rev. 1.0 History Initial release with Preliminary. Release to Final Data Sheet. 1.1. Delete Preliminary. Add 10ns & Low Power Ver. Delete 20ns speed bin Draft Data Aug. 5. 1998 Mar. 3. 1999 Remark Preliminary Final Rev. 2.0 Rev. 3.0 Apr. 24. 2000 Sep. 24. 2001 Final Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this

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