Samsung semiconductor K6R4008V1D
The K6R4008V1D is a 4,194,304-bit high-speed Static Random Access Memory organized as 524,288 words by 8 bits. The K6R4008V1D uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNG′s advanced CMOS process and designed for high-speed circuit technology.| Part No. | K6R4008V1D |
|---|---|
| Datasheet | K6R4008V1D Download |
| Manufacturer |  Samsung semiconductor |
| Description | 512Kx8 Bit High Speed Static RAM(3.3V Operating). Operated at Commercial and Industrial Temperature Ranges. |
| Buy | Stock & Price |
FEATURES
● Fast Access Time 8,10ns(Max.)● Low Power Dissipation Standby (TTL) : 20mA(Max.) (CMOS) : 5mA(Max.) Operating K6R4008V1D-08 : 80mA(Max.) K6R4008V1D-10 : 65mA(Max.)
● Single 3.3 ±0.3V Power Supply
● TTL Compatible Inputs and Outputs
● Fully Static Operation - No Clock or Refresh required
● Three State Outputs
● Center Power/Ground Pin Configuration
● Standard Pin Configuration K6R4008V1D-J : 36-SOJ-400 K6R4008V1D-K : 36-SOJ-400(Lead-Free) K6R4008V1D-T : 44-TSOP2-400BF K6R4008V1D-U : 44-TSOP2-400BF(Lead-Free)
● Operating in Commercial and Industrial Temperature range. CMOS SRAM
GENERAL DESCRIPTION
It is particularly well suited for use in high-density high-speed system applications. The K6R4008V1D is packaged in a 400 mil 36-pin plastic SOJ and 44-pin plastic TSOP type II. FUNCTIONAL BLOCK DIAGRAM Clk Gen. A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 I/O1~I/O8 Pre-Charge Circuit Row Select Memory Array 1024 Rows 512 x 8 Columns Data Cont. CLK Gen. I/O Circuit Column Select A10 A11 A12 A13 A14 A15 A16 A17 A18 CS WE OE -3- Rev.
