Download the K7A201800B datasheet PDF.
This datasheet also covers the K7A-2036 variant, as both devices belong to the same 64kx36 & 64kx32-bit synchronous pipelined burst sram family and are provided as variant models within a single manufacturer datasheet.
General Description
The K7A203600B, K7A203200B and K7A201800B are 2,359,296-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System.
Key Features
Synchronous Operation.
2 Stage Pipelined operation with 4 Burst.
On-Chip Address Counter.
Self-Timed Write Cycle.
On-Chip Address and Control Registers.
VDD= 3.3V+0.3V/-0.165V Power Supply.
VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O.
5V Tolerant Inputs Except I/O Pins.
Byte Writable Function.
Global Write Enable Controls a full bus-width write.
Full PDF Text Transcription for K7A201800B (Reference)
Note: Below is a high-fidelity text extraction (approx. 800 characters) for
K7A201800B. For precise diagrams, and layout, please refer to the original PDF.
Kx36 & 64Kx32 & 128Kx18-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No 0.0 0.1 History 1. Initial draft 1. Add tCYC 250,225, 200MHz bin. Draft Date Dec. 10. 2001 Jan . 17. 2002 Remark Preliminary Preliminary The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any queswww.DataSheet4U.com tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. www.DataS
K7A201800B Datasheet
