K7A201800B Description
The K7A203600B, K7A203200B and K7A201800B are 2,359,296-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as 64K(128K) words of 36/32(18) bits and integrates address and control registers, a 2-bit burst address counter and added some new functions for high performance cache RAM applications; Write cycles are internally...
K7A201800B Key Features
- Synchronous Operation
- 2 Stage Pipelined operation with 4 Burst
- On-Chip Address Counter
- Self-Timed Write Cycle
- On-Chip Address and Control Registers
- VDD= 3.3V+0.3V/-0.165V Power Supply
- 5V Tolerant Inputs Except I/O Pins
- Byte Writable Function
- Global Write Enable Controls a full bus-width write
- Power Down State via ZZ Signal