K7A203200A Overview
The K7A203200A is a 2,097,152-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as 64K words of 32bits and integrates address and control registers, a 2-bit burst address counter and added some new functions for high performance cache RAM applications; Write cycles are internally self-timed and synchronous.