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K7R161884B - 512Kx36 & 1Mx18 QDR II b4 SRAM

Download the K7R161884B datasheet PDF. This datasheet also covers the K7R variant, as both devices belong to the same 512kx36 & 1mx18 qdr ii b4 sram family and are provided as variant models within a single manufacturer datasheet.

General Description

Input Clock Input Clock for Output Data Output Echo Clock DLL Disable when low Address Inputs Data Inputs 1 NOTE Q0-35 W R BW0, BW1,BW2, BW3 VREF ZQ VDD VDDQ VSS TMS TDI TCK TDO NC Data Outputs Write Control Pin,active when low Read Control Pin,active when low Block Write Control Pin,active when l

Key Features

  • 1.8V+0.1V/-0.1V Power Supply.
  • DLL circuitry for wide output data valid window and future freguency scaling.
  • I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/-0.1V for 1.8V I/O.
  • Separate independent read and write data ports with concurrent read and write operation.
  • HSTL I/O.
  • Full data coherency, providing most current data.
  • Synchronous pipeline read with self timed late write.
  • Registered address, control and.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (K7R-1636.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription for K7R161884B (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for K7R161884B. For precise diagrams, and layout, please refer to the original PDF.

K7R163684B K7R161884B Document Title 512Kx36 & 1Mx18 QDRTM II b4 SRAM 512Kx36-bit,1Mx18-bit QDRTM II b4 SRAM Revision History Rev. No. 0.0 0.1 History 1. Initial document...

View more extracted text
b4 SRAM Revision History Rev. No. 0.0 0.1 History 1. Initial document. 1. Change the Boundary scan exit order. 2. Correct the Overshoot and Undershoot timing diagram. 1. Change JTAG Block diagram 1. Add the speed bin (-25) 1. Correct the JTAG ID register definition 2. Correct the AC timing parameter (delete the tKHKH Max value) 1. Change the Maximum Clock cycle time. 2. Correct the 165FBGA package ball size. 1. Add the power up/down sequencing comment. 2. Update the DC current parameter (Icc and Isb). 3. Change the Max. speed bin from -33 to -30. 1. Change the ISB1. Speed Bin -30 -25 -20 -16 1.0 2.0 1. Final spec release

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