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K9F1208U0M-YIB0 - 64M x 8 Bit NAND Flash Memory

Download the K9F1208U0M-YIB0 datasheet PDF. This datasheet also covers the K9F variant, as both devices belong to the same 64m x 8 bit nand flash memory family and are provided as variant models within a single manufacturer datasheet.

Description

The K9F1208U0M is a 64M(67,108,864)x8bit NAND Flash Memory with a spare 2,048K(2,097,152)x8bit.

Its NAND cell provides the most cost-effective solution for the solid state mass storage market.

Features

  • Voltage Supply : 2.7V~3.6V.
  • Organization - Memory Cell Array : (64M + 2,048K)bit x 8bit - Data Register : (512 + 16)bit x8bit multipled by four planes.
  • Automatic Program and Erase - Page Program : (512 + 16)Byte - Block Erase : (16K + 512)Byte.
  • 528-Byte Page Read Operation - Random Access : 12µs(Max. ) - Serial Page Access : 50ns(Min. ).
  • Fast Write Cycle Time - Program time : 200µs(Typ. ) - Block Erase Time : 2ms(Typ. ).
  • Command/Address/Data Mul.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (K9F-1208U0.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
K9F1G08B0C FLASH MEMORY Samsung
K9F1G08Q0M-PCB0 1Gb 1.8V NAND Flash Errata Samsung
K9F1G08Q0M-PIB0 1Gb 1.8V NAND Flash Errata Samsung
K9F1G08Q0M-YCB0 1Gb 1.8V NAND Flash Errata Samsung
K9F1G08Q0M-YIB0 1Gb 1.8V NAND Flash Errata Samsung

Other Datasheets by Samsung Semiconductor

Part Number Description
K9F1208U0M-YCB0 64M x 8 Bit NAND Flash Memory
K9F1208U0M- 64M x 8 Bit NAND Flash Memory
K9F1208U0 64M x 8 Bit NAND Flash Memory
K9F1208U0A NAND Flash Memory
K9F1208U0B 64M x 8 Bit NAND Flash Memory

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
K9F1208U0M-YCB0, K9F1208U0M-YIB0 Document Title 64M x 8 Bit NAND Flash Memory Revision History Revision No 0.0 FLASH MEMORY History 1. Initial issue Draft Date Oct. 27th 2000 Remark Advanced Information 0.1 1. Renamed GND input (pin # 6) on behalf of SE (pin # 6) - The SE input controls the access of the spare area. When SE is high, the spare area is not accessible for reading or programming. SE is rec ommended to be coupled to GND or Vcc and should not be toggled during reading or programming. => Connect this input pin to GND or set to static low state unless the sequential read mode excluding spare area is used. 2. Updated operation for tRST timing - If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us. 1. Changed GND input (pin # 6) pin to N.
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