KM416C254D Datasheet | Samsung Semiconductor

DESCRIPTION This is a family of 262,144 x 16 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random access of memory cells within the same row. Power supply voltage(+5.0V or +3.3V), Access time (-5,-6 or -7), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RASonly refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 256Kx16 EDO Mode DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reliability. It may be used as graphic memory unit for microputer, personal puter and portable machines. - Extended Data Out Mode operation FEATURES - Part Identification - KM416C254D/DL (5V, 512 Ref.) - KM416V254D/DL (3.3V, 512 Ref.) - 2 CAS Byte/Wrod Read/Write operation - CAS-before-RAS refresh capability - RAS-only and Hidden refresh capability - Self-refresh capability (L-ver only) - TTL(5V)/LVTTL(3.3V) patible inputs and outputs - Early Write or output enable controlled write - JEDEC Standard pinout - Available in 40-pin SOJ 400mil and 44(40)-pin packages - Triple +5V±10% power supply (5V product) - Triple +3.3V±0.3V power supply (3.3V product) - Active Power Dissipation Speed -5 -6 -7 - Refresh Cycles Part NO. C254D V254D VCC 5V 3.3V Refresh cycle 512 3.3V(512 Ref.) 255 235 Unit : m W 5V(512 Ref.) 605 495 440 FUNCTIONAL BLOCK DIAGRAM Refresh period Normal 8ms L-ver 128ms RAS UCAS LCAS W Control Clocks VBB Generator Vcc Vss Lower Data in Buffer Sense Amps & I/O Lower Data out Buffer Upper Data in Buffer Upper Data out Buffer Refresh Timer Row Decoder - Performance Range Refresh Control DQ0 to DQ7 Speed -5 -6 -7 t RAC 50ns 60ns 70ns t CAC 15ns 15ns 20ns t RC 84ns 104ns 124ns t HPC 20ns 25ns 30ns Remark 5V only 5V/3.3V 5V/3.3V A0~A8 Col. Address Buffer Refresh Counter Row Address Buffer Memory Array...