KM44S32030 Datasheet PDF - Samsung semiconductor 8M x 4Bit x 4 Banks Synchronous DRAM Specs

KM44S32030 - 8M x 4Bit x 4 Banks Synchronous DRAM

Datasheet Summary

Description

The KM44S32030 is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 8,388,608 words by 4 bits, fabricated with SAMSUNG′s high performance CMOS technology.

Features

JEDEC standard 3.3V power supply.
LVTTL compatible with multiplexed address.
Four banks operation.
MRS cycle with address key programs -. CAS Latency (2 & 3) -. Burst Length (1, 2, 4, 8) -. Burst Type (Sequential & Interleave).
All inputs are sampled at the positive going edge of the system clock.
Burst Read Single-bit Write operation.
DQM for masking.
Auto & self refresh.
64ms refresh period (4K cycle) Prelimina.

Datasheet Details

Part number	KM44S32030
Manufacturer	Samsung semiconductor
File Size	116.82 KB
Description	8M x 4Bit x 4 Banks Synchronous DRAM
Datasheet	KM44S32030 Datasheet
Additional preview pages of the KM44S32030 datasheet.

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Full PDF Text Transcription

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KM44S32030 8M x 4Bit x 4 Banks Synchronous DRAM FEATURES • JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address • Four banks operation • MRS cycle with address key programs -. CAS Latency (2 & 3) -. Burst Length (1, 2, 4, 8) -. Burst Type (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock. • Burst Read Single-bit Write operation • DQM for masking • Auto & self refresh • 64ms refresh period (4K cycle) Preliminary CMOS SDRAM GENERAL DESCRIPTION The KM44S32030 is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 8,388,608 words by 4 bits, fabricated with SAMSUNG′s high performance CMOS technology.

Published: Apr 4, 2005 |