KM44S32030B Datasheet PDF - Samsung semiconductor 128Mbit SDRAM 8M x 4Bit x 4 Banks Synchronous DRAM LVTTL Specs

KM44S32030B - 128Mbit SDRAM 8M x 4Bit x 4 Banks Synchronous DRAM LVTTL

Datasheet Summary

Description

The KM44S32030B is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 8,388,608 words by 4 bits, fabricated with SAMSUNG′s high performance CMOS technology.

Features

JEDEC standard 3.3V power supply.
LVTTL compatible with multiplexed address.
Four banks operation.
MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 Page ) -. Burst type (Sequential & Interleave).
All inputs are sampled at the positive going edge of the system clock.
Burst read single-bit write operation.
DQM for masking.
Auto & self refresh.
64ms refresh period (4K Cycle) CMO.

Datasheet Details

Part number	KM44S32030B
Manufacturer	Samsung semiconductor
File Size	135.09 KB
Description	128Mbit SDRAM 8M x 4Bit x 4 Banks Synchronous DRAM LVTTL
Datasheet	KM44S32030B Datasheet
Additional preview pages of the KM44S32030B datasheet.

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Full PDF Text Transcription

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KM44S32030B CMOS SDRAM 128Mbit SDRAM 8M x 4Bit x 4 Banks Synchronous DRAM LVTTL Revision 0.1 June 1999 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.1 Jun. 1999 KM44S32030B Revision History Revision 0.0 (May 15, 1999) CMOS SDRAM • Changed tRDL from 1CLK to 2CLK in OPERATING AC PARAMETER. • Skip ICC4 value of CL=2 in DC characteristics in datasheet. • Define a new parameter of tDAL( 2CLK +20ns), Last data in to Active delay in OPERATING AC PARAMETER. • Eliminated FREQUENCY vs.PARAMETER RELATIONSHIP TABLE.

Published: Apr 4, 2005 |