M470T2953CZ0 Datasheet | Samsung Semiconductor

Features - Performance range D6(DDR2-667) Speed@CL3 Speed@CL4 Speed@CL5 CL-t RCD-t RP 400 667 667 4-4-4 E6(DDR2-667) 400 533 667 5-5-5 D5(DDR2-533) 400 533 533 4-4-4 CC(DDR2-400) 400 400 3-3-3 Unit Mbps Mbps Mbps CK - JEDEC standard 1.8V ± 0.1V Power Supply - VDDQ = 1.8V ± 0.1V - 200 MHz f CK for 400Mb/sec/pin, 267MHz f CK for 533Mb/sec/pin, 333MHz f CK for 667Mb/sec/pin - 4 independent internal banks - Posted CAS - Programmable CAS Latency: 3, 4, 5 - Programmable Additive Latency: 0, 1 , 2 , 3 and 4 - Write Latency(WL) = Read Latency(RL) -1 - Burst Length: 4 , 8(Interleave/nibble sequential) - Programmable Sequential / Interleave Burst Mode - Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature ) - Off-Chip Driver(OCD) Impedance Adjustment - On Die Termination with selectable values(50/75/150 ohms or disable) - PASR(Partial Array Self Refresh) - Average Refesh Period 7.8us at lower a TCASE 85°C, 3.9us at 85°C < TCASE < 95 °C - support High Temperature Self-Refresh rate enable feature - Package: 60ball FBGA - 128Mx4/64Mx8 , 84ball FBGA 32Mx16 - Ro HS pliant Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram. Address Configuration Organization 64Mx8(512Mb) based Module 32Mx16(512Mb) based Module Row Address A0-A13 A0-A12 Column Address A0-A9 A0-A9 Bank Address BA0-BA1 BA0-BA1 Auto Precharge A10 A10 Rev. 1.1 Mar. 2005 256MB, 512MB, 1GB Unbuffered SODIMMs Pin Configurations (Front side/Back side) Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 DDR2...