M470T3354CZx Datasheet | Samsung Semiconductor

Features - Performance range E7 (DDR2-800) Speed@CL3 Speed@CL4 Speed@CL5 CL-t RCD-t RP 400 533 800 5-5-5 E6 (DDR2-667) 400 533 667 5-5-5 D5 (DDR2-533) 400 533 533 4-4-4 CC (DDR2-400) 400 400 3-3-3 Unit Mbps Mbps Mbps CK - JEDEC standard 1.8V ± 0.1V Power Supply - VDDQ = 1.8V ± 0.1V - 200 MHz f CK for 400Mb/sec/pin, 267MHz f CK for 533Mb/sec/pin, 333MHz f CK for 667Mb/sec/pin, 400MHz f CK for 800Mb/sec/pin - 4 Banks - Posted CAS - Programmable CAS Latency: 3, 4, 5 - Programmable Additive Latency: 0, 1 , 2 , 3 and 4 - Write Latency(WL) = Read Latency(RL) -1 - Burst Length: 4 , 8(Interleave/nibble sequential) - Programmable Sequential / Interleave Burst Mode - Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature ) - Off-Chip Driver(OCD) Impedance Adjustment - On Die Termination with selectable values(50/75/150 ohms or disable) - PASR(Partial Array Self Refresh) - Average Refresh Period 7.8us at lower than a TCASE 85°C, 3.9us at 85°C < TCASE < 95 °C - support High Temperature Self-Refresh rate enable feature - Package: 60ball FBGA - 64Mx8 , 84ball FBGA - 32Mx16 - All of Lead-free products are pliant for Ro HS Note: For detailed DDR2...