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S3C7295 - The S3C7295 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core/ SAM47 (Samsung Arrangeable M

Datasheet Summary

Description

Table 1-1.

S3C7295 Pin Descriptions Pin Name P0.0 P0.1 P0.2 P0.3 Pin Type I/O Description 4-bit I/O port.

1-bit and 4-bit read/write and test are possible.

Features

  • Memory.
  • 256 × 4-bit RAM (excluding LCD display RAM) 16,384 × 8-bit ROM Memory-Mapped I/O Structure.
  • Data memory bank 15 Power-Down Modes.
  • Idle mode (only CPU clock stops) Stop mode (main system oscillation stops) Sub system clock stop mode 8 I/O Pins.
  • I/O: 8 pins LCD Controller/Driver.
  • 44 segments and 16 common terminals (8, 12 and 16 common selectable) Internal resistor circuit for LCD bi.

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Datasheet Details

Part number S3C7295
Manufacturer Samsung semiconductor
File Size 207.71 KB
Description The S3C7295 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core/ SAM47 (Samsung Arrangeable M
Datasheet download datasheet S3C7295 Datasheet
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S3C7295/P7295 PRODUCT OVERVIEW 1 OVERVIEW PRODUCT OVERVIEW The S3C7295 single-chip CMOS microcontroller has been designed for high performance using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers). With an up-to-704-dot LCD direct drive capability, and flexible 8-bit timer/counter, the S3C7295 offers an excellent design solution for a mid-end LCD game. Up to 8 pins of the 80-pin QFP package can be dedicated to I/O. Six vectored interrupts provide fast response to internal and external events. In addition, the S3C7295's advanced CMOS technology provides for low power consumption. OTP The S3C7295 microcontroller is also available in OTP (One Time Programmable) version, S3P7295.
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