S3C72F5
Key Features
- 544 × 4-bit RAM (excluding LCD display RAM) 16,384 × 8-bit ROM Watch Timer
- Time interval generation: 0.5 s, 3.9 ms at 32768 Hz 4 frequency outputs to BUZ pin Clock source generation for LCD
- I/O: 35 pins Input only: 4 pins
- Four internal vectored interrupts Four external vectored interrupts Two quasi-interrupts
- LCD Controller/Driver
- Supports 16-bit serial data transfer in arbitrary format
- 4 interval timer functions Watch-dog timer
- Idle mode (only CPU clock stops) Stop mode (main system oscillation stops) Subsystem clock stop mode
- Programmable 16-bit timer External event counter Arbitrary clock frequency output External clock signal divider
- 8-bit transmit/receive mode 8-bit receive mode LSB-first or MSB-first transmission selectable Internal or external clock source
