K4E641612D Datasheet | Samsung Semiconductor

DESCRIPTION This is a family of 4,194,304 x 16 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption( Normal or Low power) are optional features of this family. All of this family have C A S -before-R A S refresh, R A S -only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 4Mx16 EDO Mode DRAM family is fabricated u s i n g S a m s u n g ′s a d v a n c e d C M O S p r o c e s s t o r e a l i z e h i g h b a n d - w i d t h , l o w p o w e r c o n s u m p t i o n a n d h i g h r e l i a b i l i t y . FEATURES - Part Identification - K4E661612D-TI/P(3.3V, 8K Ref.) - K4E641612D-TI/P(3.3V, 4K Ref.) - R A S-only and Hidden refresh capability - Fast parallel test mode capability - Self-refresh capability (L-ver only) - Active Power Dissipation Unit : m W Speed -45 -50 -60 8K 324 288 252 4K 468 432 396 - LVTTL(3.3V) patible inputs and outputs - Early Write or output enable controlled write - JEDEC Standard pinout - Available in Plastic TSOP(II) packages - + 3 . 3 V ±0 . 3 V p o w e r s u p p l y - I n d u s t r i a l T e m p e r a t u r e o p e r a t i n g ( - 4 0 ~ 8 5°C ) - Extended Data Out Mode operation - 2 CAS Byte/Word Read/Write operation - C A S-before-R A S refresh capability - Refresh Cycles Part NO. K4E661612D- K4E641612D Refresh cycle 8K 4K Refresh time Normal 64ms L-ver 128ms RAS UCAS LCAS W Control Clocks Vcc Vss FUNCTIONAL BLOCK DIAGRAM VBB Generator - Access mode & R A S only refresh mode : 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.) C A S - b e f o r e -R A S & H i d d e n r e f r e s h m o d e : 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.) Refresh Control Memory Array 4,194,304 x 16 Cells Refresh Timer Row Decoder S en s e A m p s & I/ O Lower Data in Buffer Lower Data out Buffer Upper Data in Buffer Upper Data out...