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K4J55323QF-GC14 - 256Mbit GDDR3 SDRAM

This page provides the datasheet information for the K4J55323QF-GC14, a member of the K4J 256Mbit GDDR3 SDRAM family.

Description

The 8Mx32 GDDR3 is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2,097,152 words by 32 bits, fabricated with SAMSUNG’s high performance CMOS technology.

Features

  • 2.0V + 0.1V power supply for device operation.
  • 2.0V + 0.1V power supply for I/O interface.
  • On-Die Termination (ODT).
  • Output Driver Strength adjustment by EMRS.
  • Calibrated output drive.
  • Pseudo Open drain compatible inputs/outputs.
  • 4 internal banks for concurrent operation.
  • Differential clock inputs (CK and CK).
  • Commands entered on each positive CK edge.
  • CAS latency : 5, 6, 7, 8 and 9 (clock).
  • Addit.

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Datasheet preview – K4J55323QF-GC14

Datasheet Details

Part number K4J55323QF-GC14
Manufacturer Samsung
File Size 1.00 MB
Description 256Mbit GDDR3 SDRAM
Datasheet download datasheet K4J55323QF-GC14 Datasheet
Additional preview pages of the K4J55323QF-GC14 datasheet.

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Full PDF Text Transcription

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K4J55323QF-GC 256M GDDR3 SDRAM 256Mbit GDDR3 SDRAM 2M x 32Bit x 4 Banks Graphic Double Data Rate 3 Synchronous DRAM with Uni-directional Data Strobe and DLL (144 - Ball FBGA) Revision 1.7 January 2005 Samsung Electronics reserves the right to change products or specification without notice. - 1 - Rev 1.7 (Jan. 2005) K4J55323QF-GC Revision History Revision 1.7 (Jan. 18 , 2005) - Added Lead Free package part number in the data sheet. 256M GDDR3 SDRAM Revision 1.6 (Dec 2 , 2004) - Changed ICC2P and ICC6 for all frequency. Separted ICC6 for -GC and -GL. Revision 1.5 (Oct 5 , 2004) - Added K4J55323QF-G(V)C15 - Timing diagram corrected on page 28 Revision 1.4 (July 9 , 2004) - Added K4J55323QF-G(V)L20 which is VDD&VDDQ=1.8V(typical) Revision 1.
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