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K7D803671B K7D801871B
Preliminary 256Kx36 & 512Kx18 SRAM
Document Title
8M DDR SYNCHRONOUS SRAM
Revision History
Rev No. Rev. 0.0
History -Initial document.
Rev. 0.1 -ZQ tolerance changed from 10% to 15%
Rev. 0.2
-Stop Clock Standby Current condition changed from VIN=VDD-0.2V or 0.2V fixed to VIN=VIH or VIH
Rev. 0.3
-VDDQ Max. changed to 2.0V SA0, SA1 defined for Boundary Scan Order
Rev. 0.5
-Deleted -HC16 part(Part Number, Idd, AC Characterisctics)
Rev. 0.6
- Absolute Maximum ratings VDDQ changed from 3.13V to 2.825V
Rev. 0.7
- LBO input level changed from High/Low to VDD/VSS - Stop Clock Standby Current condition changed
from K=Low, K=High to K=Low, K=Low - tCHQV/tCLQV changed from 0.1ns to 0.2ns for -33 part
from 0.1ns to 0.2ns for -30 part from 0.1ns to 0.
K7D801871B Datasheet
