LC895170W
Overview
- Support for double-speed operation at a 16.9344 MHz operating frequency Either SRAM (120 ns), DRAM (80 ns), or PSRAM (85 ns) can be used.
- Support for quad-speed operation at a 33.8688 MHz operating frequency SRAM (70 ns) must be used.
- On-chip 12-byte output FIFO for sub-CPU to host computer transfers
- On-chip 12-byte input FIFO for host computer to subCPU transfers
- Subcode data can be written to SRAM by connecting the CD-DSP SUB-CODE pin and the sub-CPU can read the subcode values.
- The sub-CPU can access buffer RAM through the LC895170W.
- On-chip data transfer function for buffer RAM to buffer RAM transfers
- Pseudo-SRAM (up to 128 kwords × 8 bits × 1) can be used.
- DRAM (256 kwords × 4 bits × 2, or 1 Mwords × 4 bits × 2) can be used.
- Transfer speed: 2.8 Mbytes/s (The transfer speed depends on the operating frequency.)
