S93C56B Overview
It is organized as 64-word × 16-bit, 128-word × 16-bit, 256-word × 16-bit, respectively. Each is capable of sequential read, at which time addresses are automatically incremented in 16-bit blocks. The instruction code is patible with the NM93CS46/56/66.
S93C56B Key Features
- Wide operating voltage range
- Sequential read capable
- Write disable function when power supply voltage is low
- Function to protect against write due to erroneous instruction recognition
- Endurance: 107 cycles/word- (at +25°C) write capable, 106 cycles/word- (at +85°C) 3 × 105 cycles/word- (at +105°C)
- For each address (Word: 16 bits)
- Data retention: 10 years (after rewriting 106 cycles/word at +85°C)
- S-93C46B: 1 K-bit NM93CS46 instruction code patible
- S-93C56B: 2 K-bit NM93CS56 instruction code patible
- S-93C66B: 4 K-bit NM93CS66 instruction code patible