SK10EL14W Datasheet | SEMTECH

SK10/100EL14W 1:5 Clock Distribution Chip HIGH-PER.ORMANCE PRODUCTS Description The SK10/100EL14W is a 1:5 Clock Distribution Chip designed specifically for low skew clock distribution applications. This device is fully patible with MC100EL14 and MC100LVEL14. The device can be driven by either differential or singleended ECL/PECL input signals. The SK10/100EL14W provides a VBB output for either single-ended use or DC bias for AC coupling to the device. VBB is an output pin and should be used as a bias for the EL14W as its current sink/source capability is limited. Whenever used, VBB should be bypassed to VCC via a 0.01 µF capacitor. The EL14W Features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pulldown resistor) the SEL pin will select the differential clock input. The mon Enable pin (EN- ) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids the chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flipflops are clocked on the falling edge of the input clock; therefore, all associated specification limits are referenced to the negative edge of the clock input. .eatures - Extended Supply Voltage Range: (VEE = - 5.5V to - 3.0V, VCC = 0V) or (VCC = + 3.0V to +5.5V, VEE=0V) High Bandwidth Output Transition Max. 50 ps Output-to-Output Skew (Typ. 30 ps) VBB Output Synchronous Enable/Disable Multiplexed Clock Input 75 KΩ Internal Input Pulldown Resistors New Differential Input mon Mode Range Fully patible with MC100EL14 and MC100LVEL14 ESD Protection of >4000 V Industrial Temperature Range: - 40o C to +85o C Available in 20-Pin SOIC (150 mils) Package - - - - - - - - - - - Pin Descriptions Pin CLK, CLK- SCLK EN- SEL .unction Differential Clock Inputs Scan Clock Input Sync Enable...