SK10EL15W Datasheet | SEMTECH

HIGH-PER.ORMANCE PRODUCTS Description The SK10/100EL15W is a low skew 1:4 clock distribution chips designed explicitly for low skew clock distribution applications. This device is fully patible with MC10EL15 & MC100EL15. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. If a single-ended input is to be used, the VBB output should be connected to the CLK- input and bypassed to VCC via a 0.01 µF capacitor. The EL15W provides a VBB output for either single-ended use or as a DC bias for AC coupling to the device. The VBB pin should be used only as a bias for EL15W as its current sink/source capability is limited. Whenever used, the VBB pin should be bypassed to VCC via a 0.01 µF capacitor. The EL15W Features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pull-down resistor) the SEL pin will select the differential clock input. The mon enable (EN- ) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. SK10/100EL15W 1:4 Clock Distribution .eatures - Extended Supply Voltage Range: (VEE = - 5.5V to - 3.0V, VCC = 0V) or (VCC = + 3.0V to +5.5V, VEE=0V) 50 ps Output-to-Output Skew Synchronous Enable/Disable Multiplexed Clock Input 75KΩ Internal Input Pull-Down Resistors Fully patible with MC10EL15 and MC100EL15 Specified Over Industrial Temperature Range: - 40o C to +85o C ESD Protection of >4000V Available in 16-Pin SOIC Package - - - - - - - - PIN Description Pin Name CLK SCLK EN- SEL VBB Q0–Q3, Q0-...