SK10EP111 Datasheet | SEMTECH

SEMTECH T oday's Results ...T omorrow's Vision Low-Voltage 1:10 Differential ECL/PECL/HSTL Clock Driver Preliminary Information This document contains information on a new product. The parametric information, although not fully characterized, is the result of testing initial devices. October 4, 1999 Low-Voltage 1:10 Differential ECL/PECL/HSTL Clock Driver Features - - - - - - - - 100 ps Part-to-Part Skew 35 ps Output-to-Output Skew Differential Design VBB Output Low Voltage VEE Range of - 2.375 to - 3.8V for ECL Low Voltage VCC Range of +2.375 to +3.8V for PECL and HSTL 75 KΩ Input Pulldown Resistors ECL/PECL Outputs 32 Lead LQFP Package Logic Symbol CLK0 10 0 Q0:9 1 VBB Q0- :9- Description The SK10EP111 is a low skew 1-to-10 diffferential driver, designed with clock distribution in mind. It accepts two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or single-ended if the VBB output is used. HSTL inputs can be used when the EP111 is operating under PECL conditions. The selected signal is fanned out to 10 identical differential outputs. The SK10EP111 is specifically designed, modeled, and produced with low skew as the key goal. Optimal design and layout serve to minimize gate-to-gate skew within a device, and characterization is used to determine process control limits that ensure consistent tpd distributions from lot to lot. The net result is a dependable, guaranteed low skew device. To ensure that the tight skew specification is met, it is necessary that both sides of the differential output are terminated into 50Ω, even if only one side is being used. In most applications, all ten differential pairs will be used and therefore terminated. In the case where fewer than ten pairs are used, it is necessary to terminate at least the output pairs on the same package side as the pair(s) being used on that side in order to maintain minimum skew. Failure to do this will result in small degradations of...