LH521028 Datasheet PDF - Sharp Electrionic Components CMOS 64K x 18 Static RAM Specs

LH521028 - CMOS 64K x 18 Static RAM

Datasheet Summary

Description

Figure 1.

Features

Fast Access Times: 17/20/25/35 ns.
Wide Word (18-Bits) for:.
Improved Performance.
Reduced Component Count.
Nine-bit Byte for Parity.
Transparent Address Latch.
Reduced Loading on Address Bus.
Low-Power Stand-by Mode when Deselected.
TTL Compatible I/O.
5 V ± 10% Supply.
2 V Data Retention.
JEDEC Standard Pinout.
Package: 52-Pin PLCC 52-PIN PLCC CMOS 64K × 18 Static RAM operatio.

Datasheet Details

Part number	LH521028
Manufacturer	Sharp Electrionic Components
File Size	153.75 KB
Description	CMOS 64K x 18 Static RAM
Datasheet	LH521028 Datasheet
Additional preview pages of the LH521028 datasheet.

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Full PDF Text Transcription

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LH521028 FEATURES • Fast Access Times: 17/20/25/35 ns • Wide Word (18-Bits) for: – Improved Performance – Reduced Component Count – Nine-bit Byte for Parity • Transparent Address Latch • Reduced Loading on Address Bus • Low-Power Stand-by Mode when Deselected • TTL Compatible I/O • 5 V ± 10% Supply • 2 V Data Retention • JEDEC Standard Pinout • Package: 52-Pin PLCC 52-PIN PLCC CMOS 64K × 18 Static RAM operations on the high and the low bytes. The Address Latches are transparent when ALE is HIGH (for applications not requiring a latch), and are latched when ALE is LOW. The Address Latches and the wide word help to eliminate the need for external Address busbuffers and/or latches. Write cycles occur when Chip Enable (E), SH and/or SL, and Write Enable (W) are LOW.

Published: Mar 22, 2005 |