LH521028A Overview
The LH521028 is a high-speed 1,179,648-bit CMOS SRAM organized as 64K × 18. A fast, efficient design is obtained with a CMOS periphery and a matrix constructed with polysilicon load memory cells. The LH521028 is available in a pact 52-Pin PLCC, which along with the six pairs of supply terminals, provide for reliable operation.
LH521028A Key Features
- Fast Access Times: 15/17/20/25/35 ns
- Improved Performance
- Reduced ponent Count
- Nine-bit Byte for Parity
- Transparent Address Latch
- Reduced Loading on Address Bus
- Low-Power Stand-by Mode when Deselected
- TTL patible I/O
- 5 V ± 10% Supply
- 2 V Data Retention