LH521028A Datasheet PDF - Sharp Electrionic Components CMOS 64K x 18 Static RAM Specs

LH521028A - CMOS 64K x 18 Static RAM

Datasheet Summary

Description

The LH521028 is a high-speed 1,179,648-bit CMOS SRAM organized as 64K × 18.

A fast, efficient design is obtained with a CMOS periphery and a matrix constructed with polysilicon load memory cells.

Features

Fast Access Times: 15/17/20/25/35 ns.
Wide Word (18-Bits) for:.
Improved Performance.
Reduced Component Count.
Nine-bit Byte for Parity.
Transparent Address Latch.
Reduced Loading on Address Bus.
Low-Power Stand-by Mode when Deselected.
TTL Compatible I/O.
5 V ± 10% Supply.
2 V Data Retention.
JEDEC Standard Pinout.
Package: 52-Pin PLCC.

Datasheet Details

Part number	LH521028A
Manufacturer	Sharp Electrionic Components
File Size	124.48 KB
Description	CMOS 64K x 18 Static RAM
Datasheet	LH521028A Datasheet
Additional preview pages of the LH521028A datasheet.

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Full PDF Text Transcription

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LH521028A FEATURES • Fast Access Times: 15/17/20/25/35 ns • Wide Word (18-Bits) for: – Improved Performance – Reduced Component Count – Nine-bit Byte for Parity • Transparent Address Latch • Reduced Loading on Address Bus • Low-Power Stand-by Mode when Deselected • TTL Compatible I/O • 5 V ± 10% Supply • 2 V Data Retention • JEDEC Standard Pinout • Package: 52-Pin PLCC FUNCTIONAL DESCRIPTION The LH521028 is a high-speed 1,179,648-bit CMOS SRAM organized as 64K × 18. A fast, efficient design is obtained with a CMOS periphery and a matrix constructed with polysilicon load memory cells. The LH521028 is available in a compact 52-Pin PLCC, which along with the six pairs of supply terminals, provide for reliable operation.

Published: Mar 22, 2005 |