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LH52258A - CMOS 32K x 8 Static RAM

General Description

The LH52258A is a high-speed 262,144 bit static RAM organized as 32K × 8.

A fast, efficient design is obtained with a CMOS periphery and a matrix constructed with polysilicon load memory cells.

This RAM is fully static in operation.

Key Features

  • Fast Access Times: 20/25 ns.
  • Low-Power Standby when Deselected.
  • TTL Compatible I/O.
  • 5 V ± 10% Supply.
  • Fully-Static Operation.
  • JEDEC Standard Pinout.
  • Packages: 28-Pin, 300-mil DIP 28-Pin, 300-mil SOJ.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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LH52258A FEATURES • Fast Access Times: 20/25 ns • Low-Power Standby when Deselected • TTL Compatible I/O • 5 V ± 10% Supply • Fully-Static Operation • JEDEC Standard Pinout • Packages: 28-Pin, 300-mil DIP 28-Pin, 300-mil SOJ FUNCTIONAL DESCRIPTION The LH52258A is a high-speed 262,144 bit static RAM organized as 32K × 8. A fast, efficient design is obtained with a CMOS periphery and a matrix constructed with polysilicon load memory cells. This RAM is fully static in operation. The Chip Enable (E) control permits Read and Write operations when active (LOW) or places the RAM in a low-power standby mode when inactive (HIGH). Standby power (ISB1) drops to its lowest level if E is raised to within 0.2 V of VCC. Write cycles occur when both Chip Enable (E) and Write Enable (W) are LOW.