LH532600 Datasheet | Sharp Corporation

FEATURES - 262,144 words × 8 bit organization (Byte mode) 131,072 words × 16 bit organization (Word mode) - Access time: 100 ns (MAX.) - Static operation - TTL patible I/O - Three-state outputs - Single +5 V power supply - Power consumption: Operating: 412.5 m W (MAX.) Standby: 550 µW (MAX.) - Mask-programmable control pin: Pin 1 = OE1/OE1/DC - Packages: 40-pin, 600-mil DIP 40-pin, 525-mil SOP 48-pin, 10 × 20 mm2 TSOP (Type I) DESCRIPTION The LH532600 is a 2M-bit mask-programmable ROM organized as 262,144 × 8 bits (Byte mode) or 131,072 × 16 bits (Word mode) that can be selected by BYTE input pin. It is fabricated using silicon-gate CMOS process technology. CMOS 2M (256K × 8/128K × 16) MROM PIN CONNECTIONS 40-PIN DIP 40-PIN SOP OE1/OE1/DC A7 A6 A5 A4 A3 A2 A1 A0 CE GND OE D0 D8 D1 D9 D2 D10 D3 D11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE GND D15/A-1 (LSB) D7 D14 D6 D13 D5 D12 D4 VCC 532600-1 TOP VIEW Figure 1. Pin Connections for DIP and SOP Packages CMOS 2M MROM 48 PIN TSOP (Type I) TOP VIEW BYTE A16 A15 A14 A13 A12 A11 A10 A9 A8 NC GND NC NC OE1/OE1/DC A7 A6 A5 A4 A3 A2 A1 A0 CE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 GND GND D15/A-1 D7 D14 D6 D13 D5 D12 D4 VCC VCC GND D11 D3 D10 D2 D9 D1 D8 D0 OE GND GND NOTE: Reverse bend available on request. 532600-2 Figure 2. Pin Connections for TSOP Package CMOS 2M MROM A16 32 A15 33 A14 34 A13 35 A12 36 A11 37 A10 38 A9 A8 A7 A6 39 40 2 3 29 D15 MEMORY MATRIX (262,144 x 8) (131,072 x 16) ADDRESS DECODER ADDRESS BUFFER DATA SELECTOR/OUTPUT BUFFER 27 D14 25 D13 23 D12 20 D11 18 D10 16 D9 14 D8 28 D7 26 D6 24 D5 22 D4 19 D3 17 D2 15 D1 A5 4 A4 5 A3 6 A2 7 A1 8 A0 9 COLUMN SELECTOR CE 10 CE BUFFER TIMING GENERATOR SENSE AMPLIFIER 13...