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LH5P8128 - CMOS 1M (128K x 8) Pseudo-Static RAM

Datasheet Summary

Description

The LH5P8128 is a 1M bit Pseudo-Static RAM organized as 131,072 × 8 bits.

It is fabricated using silicon-gate CMOS process technology.

Features

  • 131,072 × 8 bit organization.
  • Access times (MAX. ): 60/80/100 ns.
  • Cycle times (MIN. ): 100/130/160 ns.
  • Single +5 V power supply.
  • Power consumption: Operating: 572/385/275 mW (MAX. ) Standby (CMOS level): 1.1 mW (MAX. ).
  • TTL compatible I/O.
  • Available for auto-refresh and self-refresh modes.
  • 512 refresh cycles/8 ms.
  • Compatible with standard 1M SRAM pinout.
  • Packages: 32-pin, 600-mil DIP 32-pin, 525-mil SOP 32-pin.

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Datasheet preview – LH5P8128

Datasheet Details

Part number LH5P8128
Manufacturer Sharp Electrionic Components
File Size 116.96 KB
Description CMOS 1M (128K x 8) Pseudo-Static RAM
Datasheet download datasheet LH5P8128 Datasheet
Additional preview pages of the LH5P8128 datasheet.

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LH5P8128 FEATURES • 131,072 × 8 bit organization • Access times (MAX.): 60/80/100 ns • Cycle times (MIN.): 100/130/160 ns • Single +5 V power supply • Power consumption: Operating: 572/385/275 mW (MAX.) Standby (CMOS level): 1.1 mW (MAX.) • TTL compatible I/O • Available for auto-refresh and self-refresh modes • 512 refresh cycles/8 ms • Compatible with standard 1M SRAM pinout • Packages: 32-pin, 600-mil DIP 32-pin, 525-mil SOP 32-pin, 8 × 20 mm2 TSOP (Type I) DESCRIPTION The LH5P8128 is a 1M bit Pseudo-Static RAM organized as 131,072 × 8 bits. It is fabricated using silicon-gate CMOS process technology. A PSRAM uses on-chip refresh circuitry with a DRAM memory cell for pseudo static operation which eliminates external clock inputs, while having the same pinout as industry standard SRAMs.
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