SiT95145 Datasheet | SiTime

Description The Cascade Clk So C™ Si T95145 is a single-chip MEMS clock jitter cleaner optimized for the highest level of clock tree integration, consolidating multiple clock ICs and oscillators into a single device. Its low noise quad-PLL architecture and programmable output drivers can deliver up to 10 differential or 20 LVCMOS low jitter clock outputs. This Clk So C™ supports 4 additional clock inputs with frac N dividers, enabling virtually any input to output frequency translation configurations from 8 k Hz to 2.1 GHz. The Si T95145 integrates a Si Time third-generation Apex MEMS resonator to pletely eliminate the need for external discrete crystal references required by traditional clock generators. This integrated MEMS approach simplifies system design and improves system reliability by eliminating the clock generator’s dependency on quartz, along with all quartz related issues: - No crystal capacitive matching issues that impact clock synthesis accuracy - Always-reliable startup even at cold temperature and other harsh environmental conditions - Simpler PCB routing without noise coupling onto a crystal interface which can result in jitter degradation - No activity dips that are inherent to quartz - 10 times more vibration resistant The Si T95145 es with the panion Cascade GUI software to simplify clock tree design. The device can be shipped with a user-specified, factory pre-programmed default startup configuration. The device configuration can be re-programmed by the user in two-time-programmable non-volatile memory (NVM) during system manufacturing or in-circuit via I2C/SPI for additional BOM flexibility. Details of register mapping can be found in the Cascade Clk So C Si T9514x Register Map - Users Manual. Applications - Clock tree consolidation replacing crystal oscillators (XOs) and buffers - Low jitter clock frequency translation and generation - 10G/100G/400G Ethernet clocking - IEEE 1588 precision time protocol (PTP) - Synchronous Ethernet clock synchronization,...