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SLX24C04P - 4 Kbit 512 x 8 bit Serial CMOS EEPROMs/ I2C Synchronous 2-Wire Bus/ Page Protection Mode

Description

Serial Clock (SCL) The SCL input is used to clock data into the device on the rising edge and to clock data out of the device on the falling edge.

Features

  • Data EEPROM internally organized as 512 bytes and 32 pages × 16 bytes.
  • Page protection mode, flexible page-by-page hardware write protection.
  • Additional protection EEPROM of 32 bits, 1 bit per data page P-DIP-8-4.
  • Protection setting for each data page by writing its protection bit.
  • Protection management without switching WP pin.
  • Low power CMOS.
  • VCC = 2.7 to 5.5 V operation.
  • Two wire serial interface bus, I2C-Bus compatible.

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Full PDF Text Transcription

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Standard EEPROM ICs SLx 24C04/P 4 Kbit (512 × 8 bit) Serial CMOS-EEPROM with I2C Synchronous 2-Wire Bus and Page Protection Mode™ Data Sheet 1998-07-27 SLx 24C04/P Revision History: Previous Version: Page Page (in previous (in current Version) Version) 3 4, 5 5 5 11, 12 15 21 19 25 25 25 I2C Bus Current Version: 1998-07-27 06.97 Subjects (major changes since last revision) 3 4, 4 – 5 11, 12 15 21 24 25 25 25 Text was changed to “Typical programming time 5 ms for up to 16 bytes”. CS0, CS1 and CS2 were replaced by n.c. The paragraph “Chip Select (CS0, CS1, CS2)” was removed completely. WP = VCC protects the upper half entire memory. The erase/write cycle is finished latest after 10 8 ms. Figure 11: second command byte is a CSR and not CSW.
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