SLX24C04P Datasheet | Siemens Semiconductor Group

Standard EEPROM ICs SLx 24C04/P 4 Kbit (512 × 8 bit) Serial CMOS-EEPROM with I2C Synchronous 2-Wire Bus and Page Protection Mode™ Data Sheet 1998-07-27 SLx 24C04/P Revision History: Previous Version: Page Page (in previous (in current Version) Version) 3 4, 5 5 5 11, 12 15 21 19 25 25 25 I2C Bus Current Version: 1998-07-27 06.97 Subjects (major changes since last revision) 3 4, 4 - 5 11, 12 15 21 24 25 25 25 Text was changed to “Typical programming time 5 ms for up to 16 bytes”. CS0, CS1 and CS2 were replaced by n.c. The paragraph “Chip Select (CS0, CS1, CS2)” was removed pletely. WP = VCC protects the upper half entire memory. The erase/write cycle is finished latest after 10 8 ms. Figure 11: second mand byte is a CSR and not CSW. The write or erase cycle is finished latest after 10 4 ms. “Capacitive load …” were added. Some timings were changed. The line “erase/write cycle” was removed. Chapter 8.4 “Erase and Write Characteristics” has been added. Purchase of Siemens I2C ponents conveys the license under the Philips I2C patent to use the ponents in the I2C system provided the system conforms to the I2C specifications defined by Philips. Edition 1998-07-27 Published by Siemens AG, Bereich Halbleiter, Marketing Kommunikation, Balanstraße 73, 81541 München © Siemens AG 1998. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for ponents, not for applications, processes and circuits implemented within ponents or assemblies. The information describes the type of ponent and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens panies and Representatives worldwide (see address list). Due to technical requirements ponents may contain dangerous substances. For information on the types in question please contact your...