82S115
DESCRIPTION
The 82S 114 and 82S 115 are Schottky-clamped Read Only Memories, incorporating on-chip data output registers. They are Field-Programmable, which means that custom patterns are immediately available by following the fusing procedure given in this data sheet. The standard 82S114 and 82S115 are supplied with all outputs at logical "0". Outputs are programmed to a logic "1" level at any specified address by fusing a Ni-Cr link matrix.
The 82S114 and 82S115 are fully TTL patible, and include on-chip decoding and two chip enable inputs for ease of memory expansion. They feature
Tri-State outputs for optimization of word expansion in bussed organizations. A D-type latch is used to enable the Tri-State output drivers. In the TRANSPARENT READ mode, stored data is addressed by applying a binary code to the address inputs while holding STROBE high. In this mode the bit drivers will be controlled solely by CE 1 and CE2 lines. In the LATCHED READ mode, after the desired address is...
