DESCRIPTION
The 82S 114 and 82S 115 are Schottky-clamped Read Only Memories, incorporating on-chip data output registers. They are Field-Programmable, which means that custom patterns are immediately available by following the fusing procedure given in this data sheet. Outputs are programmed to a logic "1" level at any specified address by fusing a Ni-Cr link matrix. A D-type latch is used to enable the Tri-State output drivers. In the TRANSPARENT READ mode, stored data is addressed by applying a binary code to the address inputs while holding STROBE high. In this mode the bit drivers will be controlled solely by CE 1 and CE2 lines. In the LATCHED READ mode, after the desired address is applied and both CE 1 and CE2 are enabled, data will enter the output latches following the positive transition of STROBE, and the data out lines will be locked into their last valid state following the negative transition of STROB E. The latches will remain set and the outputs enabled until the chip is disabled and STROBE is brought high.
Signetics
