Datasheet Details
| Part number | SIS5501 |
|---|---|
| Manufacturer | Silicon Integrated System |
| File Size | 632.88 KB |
| Description | PCI/ISA Cache Memory Controller |
| Datasheet |
 SIS5501 Datasheet
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General Description
The SiS5501(PCMC) bridges between the host bus and the PCI local bus.
The SiS5501 (PCMC) monitors each cycle initiated by the CPU, and forwards it to the PCI bus if the CPU cycle does not target the local memory.
Key Features
- Supports the 51060, 56766, 73590, 815100 MHz and 75 MHz Pentium Processor Supports M1 and Other Pentium Compatible CPU Supports the Pipelined Address Mode of the Pentium or the P54C Processor Integrated Second Level ( L2 ) Cache Controller - Write Through and Write Back Cache Modes - 8 bits or 7 bits Tag with Direct Mapped Organization - Supports Standard and Burst SRAMs - Supports 64 KBytes to 2 MBytes Cache Sizes - Cache Read/Write Cycle of 3-2-2-2 or.