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SiS5596 - PCI Memory & VGA Controller

Features

  • such as direct access frame buffer and memory access latency are also supported. The system block diagram is shown in Figure 1.1. SRAM Pentium CPU Video Decoder Standard FC SiS6204 FC DDC1,2B PnP Port IDE Bus 74F04 Power,RESET 74F244 SA,14Mhz.

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Datasheet Details

Part number SiS5596
Manufacturer Silicon Integrated System
File Size 623.12 KB
Description PCI Memory & VGA Controller
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SiS5596 Pentium PCI Chipset 1. Overview SiS5596 PCI, Memory & VGA Controller SiS5513 PCI System I/O The SiS5596/5513 with built-in VGA controller is a two-chip solution for Pentium PCI/ISA system. A portion of on board DRAM is shared with the built-in VGA controller. In that way, the system cost is substantially reduced. The SiS5596/5513 two chips solution for shared memory architecture is achieved by allowing both GUI / VGA, and System DRAM controller to control system memory. For the shared memory application, the chipset always acts as the arbiter of memory bus masters. Whenever the GUI wants to access the memory bus, it requests the memory bus from the chipset first. The chipset grants the memory bus to the GUI, only if the memory bus is not needed by the chipset.
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