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SI5342 - ANY-OUTPUT JITTER ATTENUATOR/CLOCK MULTIPLIER

General Description

These jitter attenuating clock multipliers combine fourth-generation DSPLL and MultiSynth™ technologies to enable any-frequency clock generation and jitter attenuation for applications requiring the highest level of jitter performance.

Key Features

  • Generates any combination of output.
  • frequencies from any input frequency.
  • Input frequency range:.
  • Differential: 8 kHz to 750 MHz.
  • LVCMOS: 8 kHz to 250 MHz.
  • Output frequency range:.
  • Differential: up to 712.5 MHz.
  • LVCMOS: up to 250 MHz.
  • Ultra-low jitter:.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Si5345/44/42 1 0 - C H A N N E L, A N Y- F R E Q U E N C Y, A N Y- O U T P U T J I T T E R A T T E N U A T O R/ C L O C K M U L T I P L I E R Features  Generates any combination of output  frequencies from any input frequency   Input frequency range: Differential: 8 kHz to 750 MHz  LVCMOS: 8 kHz to 250 MHz  Output frequency range:  Differential: up to 712.5 MHz  LVCMOS: up to 250 MHz  Ultra-low jitter: <100 fs typ (12 kHz–20 MHz)  Programmable jitter attenuation  bandwidth from 0.1 Hz to 4 kHz    Meets G.