Description
Input Input MUX
Output
Glitch- LOS less Output
Switch1
OE Option
Synchro- Clk Dividnous OE1 er Option
Si53301-B-GM 6 output universal buffer Yes
2
6 Diff / 12
Yes
with 2:1 input mux
SE
Yes Per Bank
Yes
Per Bank
Si53302-B-GM 10 output universal buffer Yes
2 10 Diff / 20
Yes
with 2:1
Features
- include independent (synchronous) output enable, glitchless switching, LOS monitor of input clocks, output clock division, and built-in format translation. These buffers can be paired with the Si534x clocks and jitter attenuators, the Si5332 clocks, and the Si5xx oscillators to deliver end-to-end clock tree performance. KEY.
Si53303 Datasheet
