Si53365 Description
4 2.1 LVCMOS Input Termination . 4 2.3 Output Clock Termination Options . 5 2.4 AC Timing Waveforms.
Si53365 Key Features
- Low additive jitter: 120 fs rms
- Built-in LDOs for high PSRR performance
- Up to 12 LVCMOS Outputs from LVCMOS
- Frequency range: dc to 200 MHz
- Multiple configuration options
- Dual Bank option
- 2:1 Input MUX option
- RoHS pliant, Pb-free
- Temperature range: -40 to +85 °C
- Phone [781] 376-3000