Datasheet Details
| Part number | CY2SSTV16857 |
|---|---|
| Manufacturer | SpectraLinear |
| File Size | 125.53 KB |
| Description | 14-Bit Regstered Buffer |
| Datasheet |
 CY2SSTV16857 Datasheet
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General Description
This 14-bit registered buffer is designed specifically for 2.3V to 2.7V VDD operation and is characterized for operation from 0°C to + 85°C.
All inputs are compatible with the JEDEC Standard for SSTL_2, except the LVCMOS reset (RESET) input.
All outputs are SSTL_2, Class II-compatible.
Key Features
- Differential Clock Inputs up to 280 MHz.
- Supports LVTTL switching levels on the RESET pin.
- Output drivers have controlled edge rates, so no www. DataSheet4U. com external resistors are required.
- Two KV ESD protection.
- Latch-up performance exceeds 100 mA: JESD78, Class II.
- Conforms to JEDEC STD (JESD82-3) for buffered DDR DIMMs.
- 48-pin TSSOP When RESET is LOW, the differential input receivers are disabled, and undriven (floating) data,.