DESCRIPTION
The product is in a very small outline surface mount package. PIN CONFIGURATION SOT-23-3L FEATURE 3 D G S 1 2 1.Gate 2.Source 3.Drain -30V/-4.0A, RDS(ON) = 53mΩ (Typ.) @VGS = -10V -30V/-3.2A, RDS(ON) = 60mΩ @VGS = -4.5V Super high density cell design for Extremely low RDS(ON) Exceptional on-resistance and maximum DC current capability SOT-23-3L package design PART MARKING SOT-23-3L 3 A1YA 1 2 Y: Year Code A: Process Code STANSON TECHNOLOGY 120 Bentley Square, Mountain View, Ca 94040 USA STP3401M23RG 2005. V1 ST3401M23RG P Channel Enhancement Mode MOSFET -4.0A ABSOULTE MAXIMUM RATINGS
(Ta = 25℃ Unless otherwise noted ) Parameter Symbol Typical Drain-Source Voltage Gate-Source Voltage Continuous Drain CurrentTJ=150℃) TA=25℃ TA=70℃ Pulsed Drain Current VDSS VGSS ID IDM -30 ±12 -4.0 -3.2 -15 Continuous Source Current (Diode Conduction) IS Power Dissipation TA=25℃ TA=70℃ PD Operation Junction Temperature TJ -1.0 1.25 0.8 150 Storage Temperature Range TSTG -55/150 Thermal Resistance-Junction to Ambient RθJA 120 Unit V V A A A W ℃ ℃ ℃/W STANSON TECHNOLOGY 120 Bentley Square, Mountain View, Ca 94040 USA STP3401M23RG 2005.