DESCRIPTION
PIN CONFIGURATION SOP-8 FEATURE 40V/14.0A, RDS(ON) = 13mΩ (Typ.) @VGS = 10V 40V/5.0A, RDS(ON) = 15mΩ @VGS = 4.5V Super high density cell design for extremely low RDS(ON) Exceptional on-resistance and maximum DC current capability SOP-8 package design PART MARKING Y: Year Code A: week Code Q: Process Code STANSON TECHNOLOGY 120 Bentley Square, Mountain View, Ca 94040 USA Copyright © 2007, Stanson Corp. STN4480 2010. V1 STN4480 N Channel Enhancement Mode MOSFET 14.0A ABSOULTE MAXIMUM RATINGS
(Ta = 25℃ Unless otherwise noted ) Parameter Symbol Drain-Source Voltage VDSS Gate-Source Voltage Continuous Drain Current (TJ=150℃) Pulsed Drain Current TA=25℃ TA=70℃ VGSS ID IDM Continuous Source Current (Diode Conduction) Power Dissipation TA=25℃ TA=70℃ Operation Junction Temperature IS PD TJ Storgae Temperature Range TSTG Thermal Resistance-Junction to Ambient RθJA Typical 40 ±20 14.0 10.0 70 4.0 3.1 2.0 150 -55/150 59 Unit V V A A A W ℃ ℃ ℃/W STANSON TECHNOLOGY 120 Bentley Square, Mountain View, Ca 94040 USA Copyright © 2007, Stanson Corp.