SL74LV373 Datasheet | System Logic Semiconductor

OCTAL D-TYPE TRANSPARENT LATCH (3-State) SL74LV373 are patible by pinning with SL74HC373 and SL74HCT373 series. Input voltage levels are patible with standard CMOS levels. - Output voltage levels are patible with input levels of CMOS, NMOS and TTL ICS - Voltage supply range: 2.0 to 3.2 V - LOW input current: 1.0 µÀ; 0.1 µÀ at Ò = 25 °Ñ - Input current LOW/HIGH: 8 mÀ - Latch current: not less than 150 mÀ at Ò = 125 °Ñ - ESD acceptable value: not less than 2000 V as per HBM and not less than 200 V as per MM - BLOCK DIAGRAM ORDERING INFORMATION SL74LV373N Plastic DIP SL74LV373D SOIC TA = -40° to 125° C for all packages D0 D1 D2 D3 D4 D5 D6 D7 03 04 07 08 13 14 17 18 02 05 06 09 12 15 16 Q0 Q1 Q2 Q3 Q4 Q5 Q6 OE Q0 D0 D1 Q1 Q2 D2 D3 Q3 PIN ASSIGNMENT 01 02 03 04 05 20 19 18 17 16 VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 LE 06 07 08 09 10 15 14 13 12 11 Q7 LE OE Pin 20=VCC Pin 10 = GND OE L L L H FUNCTION TABLE Inputs LE H H L X Dn H L X X Output Qn H L no change Z System Logic Semiconductor ABSOLUTE MAXIMUM RATINGS- Symbol VCC IIK - 1 2 Parameter Supply voltage Input diode current Output diode current Output source or sink current VCC current GND current Power dissipation per package: Plastic DIP - 4 SOIC - 4 Storage temperature range Rating -0.5 to +5.0 ±20 ±50 ±35 ±70 ±70 750 500 -65 to +150 Unit V mÀ mÀ mÀ mÀ mÀ m W -...