SL74LV374 Datasheet | System Logic Semiconductor

OCTAL D-TIME FLIP-FLOP; POSITIVE EDGETRIGGER (3-Stat E) SL74LV374 are patible by pinning with SL74HC374 and SL74HCT374 series. Input voltage levels are patible with standard CMOS levels. - Output voltage levels are patible with input levels of CMOS, NMOS and TTL ICS. - Supply voltage range from 2.0 to 3.2 V - LOW input current: 1.0 µÀ; 0.1 µÀ at Ò = 25 °Ñ - Output current 8 mÀ - Latch current value not less than 150 mÀ at Ò = 125 °Ñ - ESD acceptable values: not less than 2000 V as per HBM, and not less than 200 V as per MM ORDERING INFORMATION SL74LV374N Plastic DIP SL74LV374D SOIC TA = -40° to 125° C for all packages BLOCK DIAGRAM 03 04 07 08 13 14 17 18 11 02 05 06 09 12 15 16 D0 D1 D2 D3 D4 D5 D6 D7 CP Q0 Q1 Q2 Q3 Q4 Q5 Q6 OE Q0 D0 D1 Q1 Q2 D2 D3 Q3 PIN ASSIGNMENT 01 02 03 04 05 20 19 18 17 16 VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CP 06 07 08 09 10 15 14 13 12 11 Q7 Pin 20=VCC Pin 10 = GND FUNCTION TABLE Inputs OE L L L H CP Dn H L X X Output Qn H L no change Z L, H, X System Logic Semiconductor ABSOLUTE MAXIMUM RATINGS- Symbol VCC IIK - 1 IOK - IO - ICC IGND PD 2 3 Parameter Supply voltage Input diode current Output diode current Output source or sink current Bus driver outputs Ground current Power dissipation per package, Plastic DIP - 4 SOIC - 4 Storage temperature range Rating -0.5 to +5.0 ±20 ±50 ±35 ±70 ±70 750 500 -65 to +150 Unit V mÀ mÀ mÀ mÀ mÀ m W Tstg -...