EV10AQ190A
Description
The Quad ADC is made up of four 10-bit ADC cores which can be considered independently (fourchannel mode) or grouped by 2 x 2 cores (two-channel mode with the ADCs interleaved two by two) or one-channel mode (where all four ADCs are all interleaved together). All four ADCs are clocked by the same external input clock signal and controlled via an industry standard SPI (Serial Peripheral Interface).
Key Features
- Single 2.5 GHz Differential Symmetrical Input Clock
- 500 mVpp Analog Input (Differential AC or DC Coupled)
- ADC Master Reset (LVDS)
- Double Data Rate Output Protocol
- LVDS Output Format
- Power Supplies: 3.3V and 1.8V (Outputs)
- Reduced Clock Induced Transients on Power Supply Pins due to BiCMOS Silicon Technology
- Power Dissipation: 1.4W per Channel
- EBGA380 Package (RoHS, 1.27 mm Pitch) PERFORMANCE
- Selectable Full Power Input Bandwidth (–3 dB) up to 3.2 GHz (4-2-1 channel mode)
