EV12AD550B Datasheet | Teledyne Technologies

EV12AD550B Dual 12-bit 1.6 GSps ADC Space Grade OVERVIEW EV12AD550 is a dual S-band capable 12-bit ADC Features intended for space applications that is built using true single core architecture per channel providing high spectral purity. With a 3d B input bandwidth up to 4.3GHz, it allows for direct digitization in S-band without frequency down-conversion. Synthetic Aperture Radar systems will also be able to operate this ADC with reduced dynamic range at frequencies beyond 5GHz (C-band) without frequency downconversion. This device includes a multiple ADC chained synchronization feature. This would help designing large array of synchronous ADCs to support the development of MIMO systems using digital or hybrid analog/digital beamforming techniques in active antennas. Multichannel applications will benefit from a cross-talk isolation between inputs in excess of 80d B and Noise Power Ratio performance of Dual channel 12-bit 1.6GSps ADC - Single core architecture ADC per channel - Differential analog input voltage: 1Vppd - Full Power Input bandwidth (-3d B): 4.3GHz - Differential clock input - Power consumption: 2.3W / channel - Power supplies: Single Rail 3.4V or Dual rail 3.4V/2.5V - Low latency output interface: LVDS DEMUX 1:1 or 1:2 - Package: Hermetic CCGA323 21x21mm / 1mm pitch, Aluminum Nitride material - SPI configuration with space protection control - Multiple ADC chained synchronization - Test mode: ramp, flash, PRBS - Control bit: parity, in-range, trigger - Clock input up to 3.2GHz 50d B in the first Nyquist zone and better than 45d B in the 4th Nyquist zone. This device es in a hermetic flip chip PERFORMANCE @ 1.5GSps CCGA323 package in Aluminum Nitride with improved thermal performance and is planned for QML-V and ESCC certification. APPLICATIONS - 4.3GHz analog input bandwidth (-3d B) - 50 d B NPR over 1st Nyquist - 47 d B NPR over 2nd...