EV12DS480AZP Datasheet | Teledyne Technologies

MAIN Features - 12-bit resolution - 6.4 GSps guaranteed conversion rate (operational up to 7 GSps) - 8.0 GSps guaranteed conversion with reduced data rate (operational up to 8.5 GSps) - - 3 d B Analog output Bandwidth of 7.5 GHz (30 ps rise and fall time on DAC output step response) - Support RF signal synthesis up to 12 GHz (X-band) - Support RF signal synthesis up to 24 GHz (with reduced output power) - 4:1 or 2:1 integrated parallel MUX (selectable) - Selectable output modes: Return To Zero (RTZ), Non Return to Zero (NRZ), Narrow Return To Zero (NRTZ) and Radio Frequency (RF) - Low latency time: 3 clock cycles - 2.6 Watt Power Dissipation (in 4:1 MUX) - 3 Wires Serial Interface - LVDS differential data input and DSP clock output. - Functions: - Selectable MUX ratio 4:1 (up to 8.0 GSps), 2:1 (up to 3.2 GSps) - User-friendly functions, digitally controlled through a 3WSI serial interface: - Gain Adjustment - Output clock division selection (possibility to change the division ratio of the DSP clock) (OCDS) - Reshaped Pulse Width (RPW) and Reshaped Pulse Begin (RPB) adjustments for performance optimization - Clock phase shift select for synchronization with DSP (PSS[2:0]) - Input Under Clocking Mode by 1/2/4 (IUCM) - Direct access available for bit OCDS and PSS - Input data check bit for timing interface with FPGA check (IDC) - Timing violation flag (setup or hold) for FPGA - munication monitoring (TVF) Low power 12-bit 8GSps Digital to Analog Converter with 4/2:1 Multiplexer Datasheet DS 60S 217580 rev A.1 - Analog output differential swing: 1Vpp (100Ω differential impedance) - External SYNC that can be used for synchronization of multiple DACs - Power supplies: 3.3 V (Digital), 3.3V & 5V...