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THC63LVD824A - LVDS Receiver

General Description

The THC63LVD824A receiver is designed to support Single Link transmission between Host and Flat Panel Display up to SXGA resolutions and Dual Link transmission between Host and Flat Panel Display up to UXGA resolutions.

Key Features

  • Wide dot clock range: 25-170MHz suited for VGA.

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Datasheet Details

Part number THC63LVD824A
Manufacturer THine Electronics
File Size 138.03 KB
Description LVDS Receiver
Datasheet download datasheet THC63LVD824A Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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THC63LVD824A _Rev1.20_E THC63LVD824A Single(112MHz)/Dual(170MHz) Link LVDS Receiver for XGA/SXGA/SXGA+/UXGA General Description The THC63LVD824A receiver is designed to support Single Link transmission between Host and Flat Panel Display up to SXGA resolutions and Dual Link transmission between Host and Flat Panel Display up to UXGA resolutions. The THC63LVD824A converts the LVDS data streams back into 48bits of CMOS/TTL data with falling edge or rising edge clock for convenient with a variety of LCD panel controllers. In Single Link, data transmit clock frequency of 112MHz, 48bits of RGB data are transmitted at an effective rate of 784Mbps per LVDS channel. Using a 112MHz clock, the data throughput is 392Mbytes per second.